Job Vacancy Analog/Custom Layout Design Engineer Cadence Design Systems

Job title: Analog/Custom Layout Design Engineer

Company: Cadence Design Systems

Job description: At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

​Cadence promotes a high-performance culture where employees can work on cutting-edge technology in an environment that encourages them to be creative, innovate, and make an impact while working alongside the industry’s brightest people and innovating for the most advanced companies globally. Through Cadence’s Electronic Design Automation (EDA) products, we’ve worked with a wide range of customers, from helping build the world’s most powerful supercomputer to innovating in artificial intelligence and machine learning. Cadence has been voted as a Great Place to Work globally and in the United States and is also a Fortune 100 Best Companies to Work For 8 times.

Join our team of layout designers creating challenging IP designs for the consumer, industrial, and automotive markets. Our designs are fabricated in the world’s leading-edge silicon processes for companies ranging from large multinational companies to hot start-ups. Learn on-the-job how to apply your engineering background to create these robust, high-performance analog designs. Working with experienced, skilled designers, you will use Cadence design tools to be part of the design team. We are looking for a layout engineer capable of producing quality layouts of analog/mixed-signal circuit blocks and collaborating with circuit designers. Responsibilities include all facets of the back-end flow, from initial floor planning to detailed layout and final conformance verification to foundry design rules.

Competence in the following

Expertise in Cadence Virtuoso custom/analog layout platform

Knowledge of layout techniques for device matching, minimizing parasitics, high-speed routing

Good understanding of parasitic RC delay, signal integrity, and EM Deep sub-micron CMOS layout experience 7nm and smaller geometries

Thorough understanding of layout dependent effects on the circuit

Methods of solving advanced layout verification issues on leading foundry flows

Chip planning and block implementation

Ability to estimate layout schedule for a given circuit, plan layout, provide early feedback to circuit design engineers, etc.

We’re doing work that matters. Help us solve what others can’t.

Expected salary:

Location: San Jose, CA

Job date: Sun, 10 Jul 2022 01:03:57 GMT

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